“N2 (2nm) node entered volume production in Q1 2026, with HPC customers (Apple, NVIDIA, AMD) as launch customers. N2 uses ~14 EUV layers per wafer vs. ~10 at N3 — each node adds EUV intensity. TSMC guided N2 revenue to represent over 10% of wafer revenue by Q4 2026, tracking ahead of N3's adoption pace.”
“CoWoS advanced packaging capacity growing at 80% CAGR, still falling short of demand. TSMC confirmed demand for CoWoS "significantly exceeds" supply through 2027. TSMC is expanding CoWoS capacity in both Taiwan and the US (Arizona), but new capacity takes 18–24 months to qualify. NVIDIA alone reserves ~60% of available output.”
“HPC platform — AI accelerators, server CPUs, custom ASICs — reached 55%+ of TSMC revenue in Q1 2026, up from 42% two years ago. AI-driven HPC is structurally shifting TSMC's revenue mix toward its highest-ASP products. Management guided HPC to remain the dominant growth driver through at least 2028.”
“TSMC Arizona (Fab 21) Phase 1 (N4 process) ramping with Apple and NVIDIA as anchor customers. Phase 2 (N2) on track for 2026 construction. CHIPS Act funding ($6.6B grant) supporting capex. US-made wafers commanding 10–15% premium over Taiwan production — which customers are accepting for supply chain resilience.”
“Geopolitical risk remains the key overhang for TSMC. Taiwan Strait tensions and US export control expansion create uncertainty for long-term capital allocation. TSMC management noted that geographic diversification (Arizona, Japan, Germany) is a direct response to customer requests for supply chain resilience — not purely an economic decision.”