Advanced packaging TAM is growing faster than any other semiconductor segment because demand compounds from two directions simultaneously: more chips per package (chiplets, HBM stacks) and larger die area per generation. The base case reflects CoWoS growing at 80% CAGR while broader advanced packaging (FOPLP, fan-out, SiP) grows at 20–25%. TSMC captures the highest-value portion; OSATs capture volume at lower ASP. Bear case assumes FOPLP or a new substrate technology disrupts CoWoS economics earlier than expected, compressing TSMC's packaging ASP premium. Bull case assumes every major AI chip roadmap continues to add chiplet complexity and HBM stack count, keeping advanced packaging on the critical path with no viable alternative at scale before 2030.
“NVIDIA has reserved approximately 60% of TSMC's total CoWoS output through 2027, leaving rival AI chip makers scrambling for allocation. CoWoS capacity is growing at 80% CAGR and still falling short of demand. Advanced packaging — not silicon fab — is now the binding constraint on AI chip output.”
“GPU die area is compounding packaging demand across generations: Hopper substrate 3,190mm², Blackwell 5,913mm², Rubin estimated at 8,051mm². Each generation requires a larger CoWoS interposer. TSMC earns packaging revenue that scales with area — not just unit count — making this a structural ASP tailwind.”
“HBM bonding to GPU logic die is performed via advanced packaging (hybrid bonding, through-silicon vias). Every HBM3E or HBM4 stack must be co-packaged with the accelerator die using CoWoS. As HBM stacks per chip increase — GB300 uses 8 stacks vs. H100's 6 — packaging complexity and area grow non-linearly.”
“TSMC SoIC (System on Integrated Chips) face-to-face and face-to-back stacking enabling chiplet architectures for AMD EPYC, Apple M-series, and upcoming NVIDIA designs. Chiplet adoption is structural — it allows mixing process nodes and extending Moore's Law economics — making advanced packaging a permanent cost of every leading-edge chip.”
“OSAT players ASE Group and Amkor are racing to qualify CoWoS-equivalent processes. Both have announced capacity investments, but qualification timelines at key customers (NVIDIA, AMD, Broadcom) are running 18–24 months. Meaningful volume from non-TSMC advanced packaging sources is unlikely before late 2027.”
“Panel-level packaging (FOPLP) under development at Samsung and ASE could eventually reduce advanced packaging cost 30–40% vs. wafer-level CoWoS, by using larger glass or PCB panels instead of silicon wafers. Samsung targeting first production-ready FOPLP for 2028. If successful, it breaks TSMC's packaging stranglehold.”
NVIDIA has reserved approximately 60% of TSMC's total CoWoS capacity through 2027, leaving every other AI chip maker — AMD, Broadcom, Marvell, hyperscaler custom ASICs — competing for the remaining 40%. This is not a market dynamic; it is a deliberate supply chain capture. Rivals building AI clusters must either wait for TSMC to expand, qualify at an OSAT (18–24 months away), or redesign their chip to avoid CoWoS (not possible at current die sizes).
AMD EPYC, Intel Xeon, Apple M-series, Qualcomm Oryon, and nearly every next-generation data center chip are chiplet-based. Chiplets require advanced packaging to bond multiple dies — there is no way to build a modern high-performance processor without it. This makes advanced packaging a structural cost of every leading-edge chip, not a niche technology. The total addressable chip count that needs advanced packaging is expanding from AI accelerators to CPUs to networking ASICs simultaneously.
Each generation of GPU increases the number of HBM stacks per chip: H100 used 6 stacks, GB300 uses 8, next-generation Rubin is expected to use 12. Every additional stack requires more CoWoS interposer area and more precision bonding. The packaging step does not just scale linearly — it gets harder and more expensive with each generation, compounding TSMC's pricing power and extending lead times.
Fan-Out Panel Level Packaging (FOPLP) uses large glass or PCB panels instead of silicon wafers, potentially reducing advanced packaging cost by 30–40% and breaking TSMC's near-monopoly. Samsung is targeting first production-ready FOPLP for 2028; ASE is investing in panel infrastructure. The key risk for TSMC: if FOPLP achieves acceptable yield at customer-qualifying scale, it creates an alternative supply chain that did not exist before. This is the bear case for CoWoS ASP growth post-2028.